The present invention relates to an array substrate and a method of manufacturing the same.
A liquid crystal display (LCD) is one type of flat panel displays (FPD). Based on the electrical field used to drive liquid crystal, liquid crystal display devices can be categorized into a vertical electric field type and a horizontal electric field type. Horizontal field type liquid crystal display devices can be further categorized into a fringe field switching (FFS) type and an in-plane switching (IPS) type.
FIG. 1 is the schematic view of an array substrate after a first patterning process of a manufacturing method. FIG. 2 is the schematic view of the array substrate after a second patterning process of the manufacturing method. FIG. 3a is the schematic view of the array substrate after a third patterning process of the manufacturing method. FIG. 3b is the cross-sectional view of a “α region” after depositing a second insulating layer during the third patterning process of the manufacturing method. FIG. 3c is the cross-sectional view of the α region after a developing process during the third patterning process of the manufacturing method. FIG. 3d is the cross-sectional view of the α region after an etching process during the third patterning process of the manufacturing method. FIG. 3c is the cross-sectional view of the α region after an ashing process during the third patterning process of the manufacturing method. FIG. 3f is the cross-sectional view of the α region after depositing a pixel electrode layer during the third patterning process of the manufacturing method. FIG. 3g is the cross-sectional view of the α region after lifting-off process during the third patterning process of the manufacturing method.
As shown in FIG. 1 to FIG. 3g, to reduce the cost and increase the yield, the method of manufacturing an array substrate of a liquid crystal display device using three patterning processes comprises the following steps.
During the first patterning process, depositing a first metal layer and patterning it into a gate line 1 and a common electrode line 2 through a full tone mask.
During the second patterning process, sequentially depositing a first insulating layer, a semiconductor layer, a heavily doped n+ type semiconductor layer, and a second metal layer. The lamination of the semiconductor layer and the heavily doped n+ type semiconductor layer is used for forming an active layer in the thin film transistor. An active layer 4, a channel of the thin film transistor, a data line 5, a source electrode 51, and a drain electrode 52 are formed through a dual tone mask.
During the third patterning process, depositing a second insulating layer 6, forming a via hole through a dual tone mask, ashing the remaining photoresist 8, depositing a pixel electrode layer, and forming a pixel electrode after lifting off the remaining photoresist.
During forming of the pixel electrode through the lifting-off process in the third patterning process, to assure that the lifting-off process works, the first and the second insulating layers need to be over-etched with a dry method, so as to form a rift section of the pixel electrode layer. However, the time of over-etching should be closely watched. If the time is too short, the rift section of the pixel electrode layer will not be obtained, and if it is too long, the common electrode line under the gate insulating layer will be exposed, which leads to defects in the electrical connection between the formed pixel electrode and the common electrode line. Accordingly, during depositing of the pixel electrode layer, the effort to secure the rift section causes defects in the electrical connection between the formed pixel electrode and the common electrode line.